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16-bit 1 msps pulsar ? unipolar adc with reference ad7667 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features 2.5 v internal reference: typical drift 3 ppm/c guaranteed max drift 15 ppm/c throughput: 1 msps (warp mode) 800 ksps (normal mode) 666 ksps (impulse mode) inl: 2.0 lsb max (0.0038% of full scale) 16-bit resolution with no missing codes s/(n+d): 88 db min @ 20 khz thd: C96 db max @ 20 khz analog input voltage range: 0 v to 2.5 v no pipeline delay parallel and serial 5 v/3 v interface spi ? /qspi tm /microwire tm /dsp compatible single 5 v supply operation power dissipation 87 mw typ @ 666 ksps, 130 w @ 1 ksps without ref 133 mw typ @1 msps with ref 48-lead lqfp and 48-lead lfcsp packages pin-to-pin compatible with ad7671, ad7677 applications data acquisition medical instruments digital signal processing battery-powered systems process control general description the ad7667* is a 16-bit, 1 msps, charge redistribution sar analog-to-digital converter that operates from a single 5 v power supply. the part contains a high speed 16-bit sampling adc, an internal conversion clock, internal reference, error correction circuits, and both serial and parallel system inter- face ports. it features a very high sampling rate mode (warp), a fast mode (normal) for asynchronous applications, and a reduced power mode (impulse) for low power applications where power is scaled with the throughput. the ad7667 is hardware factory-calibrated and comprehensively tested to ensure ac parameters such as signal-to-noise ratio (snr) and total harmonic distortion (thd) in addition to the more traditional dc parameters of gain, offset, and linearity. operation is specified from C40c to +85c. *patent pending. functional block diagram 03035-0-001 switched cap dac 16 control logic and calibration circuitry clock ad7667 data[15:0] busy rd cs ser/par ob/2c ognd ovdd dgnd dvdd avdd agnd ref refgnd in ingnd pd reset serial port parallel interface cnvst warp impulse ref refbufin pdbuf pdref byteswap figure 1. table 1. pulsar selection type/ksps 100C250 500C570 800C 1000 pseudo- differential ad7651 ad7660 / ad7661 ad7650 / ad7652 ad7664 / ad7666 ad7653 ad7667 true bipolar ad7663 ad7665 ad7671 true differential ad7675 ad7676 ad7677 18-bit ad7678 ad7679 ad7674 multichannel/ simultaneous ad7654 ad7655 product highlights 1. fast throughput. the ad7667 is a 1 msps, charge redistribution, 16-bit sar adc with internal error correction circuitry. 2. superior inl. the ad7667 has a maximum integral nonlinearity of 2.0 lsbs with no missing 16-bit codes. 3. internal reference. the ad7667 has an internal reference with a typical temperature drift of 3 ppm/c. 4. single-supply operation. the ad7667 operates from a single 5 v supply. in impulse mode, its power dissipation decreases with throughput. 5. serial or parallel interface. versatile parallel or 2-wire serial interface arrangement is compatible with both 3 v and 5 v logic.
ad7667 rev. 0 | page 2 of 28 table of contents specifications ..................................................................................... 3 timing specifications ....................................................................... 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 definitions of specifications ......................................................... 11 typical performance characteristics ........................................... 12 circuit information ........................................................................ 16 converter operation .................................................................. 16 typical connection diagram ................................................... 18 power dissipation versus throughput .................................... 20 conversion control .................................................................... 21 digital interface .......................................................................... 22 parallel interface ......................................................................... 22 serial interface ............................................................................ 22 master serial interface ............................................................... 23 slave serial interface .................................................................. 24 microprocessor interfacing ....................................................... 26 application hints ........................................................................... 27 bipolar and wider input ranges .............................................. 27 layout .......................................................................................... 27 evaluating the ad7667s performance .................................... 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history revision 0: initial version.
ad7667 rev. 0 | page 3 of 28 specifications table 2. C40c to +85c, avdd = dvdd = 5 v, ov dd = 2.7 v to 5.25 v, unless otherwise noted. parameter conditions min typ max unit resolution 16 bits analog input voltage range v in C v ingnd 0 v ref v operating input voltage v in C0.1 +3 v v ingnd C0.1 +0.5 v analog input cmrr f in = 100 khz 64 db input current 1 msps throughput 19 a input impedance 1 throughput speed complete cycle in warp mode 1 s throughput rate in warp mode 1 1000 ksps time between conversions in warp mode 1 ms complete cycle in normal mode 1.25 s throughput rate in normal mode 0 800 ksps complete cycle in impulse mode 1.5 s throughput rate in impulse mode 0 666 ksps dc accuracy integral linearity error C2.0 +2.0 lsb 2 no missing codes 16 bits differential linearity error C1.0 +1.5 lsb transition noise 0.7 lsb unipolar zero error, t min to t max 3 25 lsb unipolar zero error temperature drift 1.0 ppm/c full-scale error, t min to t max 3 ref = 2.5 v 0.08 % of fsr full-scale error temperature drift 1.0 ppm/c power supply sensitivity avdd = 5 v 5% 2 lsb ac accuracy signal-to-noise f in = 20 khz 88 89.2 db 4 spurious free dynamic range f in = 20 khz 96 105 db total harmonic distortion f in = 20 khz C104 C96 db signal-to-(noise + distortion) f in = 20 khz 88 89 db C60 db input, f in = 20 khz 30 db C3 db input bandwidth 13 mhz sampling dynamics aperture delay 2 ns aperture jitter 5 ps rms transient response full-scale step 250 ns reference internal reference voltage v ref @ 25c 2.493 2.5 2.507 v internal reference temperature drif t C40c to +85c 3 15 ppm/c output voltage hysteresis C40c to +85c 50 ppm long-term drift 100 ppm/1000 hours line regulation avdd = 5 v 5% 15 ppm/v turn-on settling time c ref = 10 f 5 ms temperature pin voltage output @ 25c 300 mv temperature sensitivity 1 mv/c output resistance 4 k? external reference voltage range 2.3 2.5 avdd C 1.85 v external reference current drai n 1 msps throughput 242 a
ad7667 rev. 0 | page 4 of 28 parameter conditions min typ max unit digital inputs logic levels v il C0.3 +0.8 v v ih 2.0 dvdd + 0.3 v i il C1 +1 a i ih C1 +1 a digital outputs data format 5 pipeline delay 6 v ol i sink = 1.6 ma 0.4 v v oh i source = C500 a ovdd C 0.6 v power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 7 v operating current 8 1 msps throughput avdd 9 with reference and buffer 18.7 ma avdd 10 reference and buffer alone 3 ma dvdd 11 7.8 ma ovdd 11 200 a power dissipation without ref 9, 11 666 ksps throughput 87 115 mw 1 ksps throughput 130 w power dissipation with ref 8, 9 1 msps throughput 133 145 mw temperature range 12 specified performance t min to t max C40 +85 c 1 see analog input section. 2 lsb means least significant bit. with the 0 v to 2.5 v input range, 1 lsb is 38.15 v. 3 see definitions of specifications section. these specifications do not include the error contribution from the external referen ce. 4 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full-scale, unless otherwise specified. 5 parallel or serial 16-bit. 6 conversion results are available imme diately after completed conversion. 7 the max should be the minimu m of 5.25 v and dvdd + 0.3 v. 8 in warp mode. 9 with ref, pdref and pdbuf are low; wi thout ref, pdref and pdbuf are high. 10 with pdref, pdbuf low and pd high. 11 impulse mode. tested in parallel reading mode 12 consult factory for extended temperature range.
ad7667 rev. 0 | page 5 of 28 timing specifications table 3. C40c to +85c, avdd = dvdd = 5 v, ov dd = 2.7 v to 5.25 v, unless otherwise noted. parameter symbol min typ max unit refer to figure 33 and figure 34 convert pulse width t 1 10 ns time between conversions (warp mode/normal mode/impulse mode) 1 t 2 1/1.25/1.5 s cnvst low to busy high delay t 3 35 ns busy high all modes except master serial read after convert t 4 0.75/1/1.25 s aperture delay t 5 2 ns end of conversion to busy low delay t 6 10 ns conversion time t 7 0.75/1/1.25 s acquisition time t 8 250 ns reset pulse width t 9 10 ns refer to figure 35, figure 36, and figure 37 (parallel interface modes) cnvst low to data valid delay t 10 0.75/1/1.25 s data valid to busy low delay t 11 12 ns bus access request to data valid t 12 45 ns bus relinquish time t 13 5 15 ns refer to figure 39 and figure 40 (master serial interface modes) 2 cs low to sync valid delay t 14 10 ns cs low to internal sclk valid delay 2 t 15 10 ns cs low to sdout delay t 16 10 ns cnvst low to sync delay t 17 25/275/525 ns sync asserted to sclk first edge delay t 18 3 ns internal sclk period 3 t 19 25 40 ns internal sclk high 3 t 20 12 ns internal sclk low 3 t 21 7 ns sdout valid setup time 3 t 22 4 ns sdout valid hold time 3 t 23 2 ns sclk last edge to sync delay 3 t 24 3 ns cs high to sync hi-z t 25 10 ns cs high to internal sclk hi-z t 26 10 ns cs high to sdout hi-z t 27 10 ns busy high in master serial read after convert 3 t 28 see table 4 cnvst low to sync asserted delay t 29 0.75/1/1.25 s sync deasserted to busy low delay t 30 25 ns refer to figure 41 and figure 42 (slave serial interface modes) 2 external sclk setup time t 31 5 ns external sclk active ed ge to sdout delay t 32 3 18 ns sdin setup time t 33 5 ns sdin hold time t 34 5 ns external sclk period t 35 25 ns external sclk high t 36 10 ns external sclk low t 37 10 ns 1 in warp mode only, the time between conversions is 1ms; otherwise there is no required maximum time. 2 in serial interface modes, the sync, sclk, an d sdout timings are defined with a maximum load c l of 10 pf; otherwise, the load is 60 pf maximum. 3 in serial master read during convert mode. see table 4 for serial master read after convert mode.
ad7667 rev. 0 | page 6 of 28 table 4. serial clock timings in master read after convert divsclk[1] 0 0 1 1 divsclk[0] symbol 0 1 0 1 unit sync to sclk first edge delay minimum t 18 3 17 17 17 ns internal sclk period minimum t 19 25 50 100 200 ns internal sclk period maximum t 19 40 70 140 280 ns internal sclk high minimum t 20 12 22 50 100 ns internal sclk low minimum t 21 7 21 49 99 ns sdout valid setup time minimum t 22 4 18 18 18 ns sdout valid hold time minimum t 23 2 4 30 80 ns sclk last edge to sync delay minimum t 24 3 55 130 290 ns busy high width maximum t 24 1.5 2 3 5.25 s
ad7667 rev. 0 | page 7 of 2 8 absolute maximum ra tings table 5. ad76 67 stress ratings 1 p a r a m e t e r r a t i n g in 2 , temp 2 , ref, refbufin, ingnd, r e fgnd to agnd avdd + 0.3 v to agnd C 0.3 v ground voltage differences agnd, dgn d, ognd 0.3 v supply voltages avdd, dvdd, ovdd C0.3 v to +7 v avdd to d v dd, avdd to ovdd 7 v dvdd to ovdd C0.3 v to +7 v digital inputs C0.3 v to dv dd + 0.3 v pdref, pdbuf 3 20 ma internal power dissip a tion 4 700 mw internal power dissip a tion 5 2.5 w junction tempe r ature 150c storage temperature range C65c to +150c lead temperature range (sol dering 10 s e c) 300c 1 st re sse s a b ov e t h o se li st e d un d e r abs o lut e ma xi m u m r a t i n gs m a y ca use permanent d amage to the d e vice. this is a s t ress rating onl y; functional o p e r atio n o f the device at the s e o r any o the r co nd itio ns a b o v e tho se l i s t e d in the o p e r atio nal se ctio ns of this s p e c i f ication is not impl i ed . e x pos u re to abs o l u te maximum rating co nd itio ns fo r exte nd ed pe ri od s m a y a f fect devi ce rel iabil ity. 2 se e s e ct ion . an alog in put 3 s e e the vo l t age ref e re nce input se ctio n. 4 specif ication is f o r the d e vice in f r ee ai r: 48-lead lqfp; ja = 91c/w , jc = 30c/ w. 5 specif ication is f o r the d e vice in f r ee ai r: 48-lead lfcsp; ja = 26 c/w i oh 500 a 1.6ma i ol t o output pin 1.4v c l 60pf * * in serial interf a ce modes, the sync, sclk, and sdout timings are defined with a maximum lo ad c l of 10pf; o t her wise, the lo ad is 60pf maximum. 03033-0-002 f i gure 2 . l o a d cir c ui t fo r di g i ta l inter f a c e t i mi ng , sdout , sy nc, scl k o u tputs c l = 10 p f 0.8v 2v 2v 0.8v 0.8v 2v t dela y t dela y 03033-0-003 f i gure 3. v o ltag e r e ferenc e l e vels fo r t i ming esd c a ution esd (electrostatic discharge) sensitive device. ele c trostatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge without detection. although this product features proprietar y esd protection circuitry, permanent damage may occur on devices subjected to high energy electro s tatic discha rge s . therefore, pro p er esd precautions are recommended to avoid perform a nce degradatio n or los s of functionality.
ad7667 rev. 0 | page 8 of 2 8 pin conf igura t ion and fu nction descriptions 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) agnd cnvst pd reset cs rd dgnd agnd avdd nc byteswap ob/2c warp impulse nc = no connect ser/ par d0 d1 busy d15 d14 d13 ad7667 d3/divsclk1 d12 d4 /e x t / i nt d 5 /in vsyn c d6/invscl k d7 /rdc/s d i n ognd ovdd dv dd dgnd d8 /s dout d9 /s cl k d 10/syn c d1 1 / rde rror p dbuf p dre f re fbufin temp av dd in agnd agnd nc ingnd re fgnd re f 03035-0-004 d2/divsclk0 f i g u re 4. 48-l e ad l qfp (st - 4 8 ) and 48 -l ead lfcs p (c p - 4 8 ) ta ble 6. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic type 1 description 1, 36, 41, 42 agnd p analog power g r ound pin. 2, 44 avdd p input analog power pin. nominally 5 v. 3, 40 nc no connect. 6 w a r p d i mode selection. when this pin is high and the i m pulse pin is l o w, this input selects the fastest mode, the maxi mum throughput is achievable, and a minimum conversi on rate must be applie d in order to guarantee full specified accuracy. when low, full accuracy is maintaine d independent of the minimum conve r sion rate. 7 i m p u l s e d i mode selection. when impulse is high and wa rp is low, this input selects a re duced power mode. in this mode, the power diss ipat ion is ap pr o x im ately proportio n al to the samp li ng rate. 4 b y t e s w a p d i paralle l m o d e selection ( 8 -/16- bit) . when low, the lsb is output on d[7:0] and the msb is output on d[15:8]. when h i gh, the lsb is output on d[1 5 :8 ] and the msb is output on d[7:0 ] . 5 ob/ 2c di straight binary/binary twos complement. whe n ob/ 2c is high, t h e digital output is straight binary; when low, the msb is inverted, resulting in a twos complement output from its i n ternal sh ift register. 8 ser/ par di serial/pa r al lel s e lection input. when low, the paral l el port is selected; when h i gh, the serial in terface mod e is sele cted and some bits of th e data bus are used as a se rial port. 9, 10 d[0:1] do bit 0 and bit 1 of the parallel po rt data output bu s. when ser/ par is high, these outputs are in high impedance. 11, 12 d[2:3]or divsclk[0:1] di/o when ser/ par is low, these output s are used as bit 2 and bit 3 of th e parallel port data output bus. when ser/ par is high, ext/ int is low, and rdc/sdin is low (seria l m a ster read after convert), these inputs, part of the seria l port, ar e used to slow d o wn, if d e sired , the in ternal seri al clo c k that clo c ks the data output. in other serial mo des, these pin s ar e not used. 13 d4 or ext/ int di/o when ser/ par is low, this output is us ed as bit 4 of the parallel port data output bu s. when ser/ par is high, this input, part of the serial port, is used as a digital select i n put for choosi n g the internal data clock or an ext e rnal data cl ock. with ex t/ int tied l o w, the internal clock is selected on the sclk output. with ex t/ int set to a logic high, output data i s synchro n ized to an externa l cl ock signal connected to the sclk in put. 14 d5 or invsync di/o when ser/ par is low, this output is us ed as bit 5 of the parallel port data output bu s. when ser/ par is high, this input, part of the serial port, is used to select the active state of the sync signal. it is activ e in both master and slave mod e s. when low, sync is active high. when high, sync is active low. 15 d6 or invsclk di/o when ser/ par is low, this output is us ed as bit 6 of the parallel port data output bu s. when ser/ par is high, this input, part of the serial port, is used to invert the sclk signal. it is active in both master an d slave mod e s.
ad7667 rev. 0 | page 9 of 28 pin no. mnemonic type 1 description 16 d7 or rdc/sdin di/o when ser/ par is low, this output is us ed as bit 7 of the parallel port data output bus. when ser/ par is high, this input, part of the serial port, is used as either an ex ternal data input or a read mode selection input depending on the state of ext/ int . when ext/ int is high, rdc/sdin could be used as a data input to daisy-chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on data with a delay of 16 sclk periods after the initiation of the read sequence. when ext/ int is low, rdc/sdin is used to select the read mode. when rdc/sdin is high, the data is output on sdout during conversion. when rdc/sdin is low, the data can be output on sdout only when the conversion is complete. 17 ognd p input/output interface digital power ground. 18 ovdd p input/output interface digital power. nominally at the same supply as the host interface (5 v or 3 v). 19 dvdd p digital power. nominally at 5 v. 20 dgnd p digital power ground. 21 d8 or sdout do when ser/ par is low, this output is us ed as bit 8 of the parallel port data output bus. when ser/ par is high, this output, part of the serial port, is used as a serial data output synchronized to sclk. conversion results are stored in an on -chip register. the ad7667 provides the conversion result, msb first, from its internal shift register. the data format is determined by the logic level of ob/ 2c . in serial mode when ext/ int is low, sdout is valid on both edges of sclk. in serial mode when ext/ int is high, if invsclk is low, sdout is update d on the sclk rising edge and valid on the next falling edge; if invsclk is high, sdout is upda ted on the sclk falling edge and valid on the next rising edge. 22 d9 or sclk di/o when ser/ par is low, this output is used as bit 9 of the parallel po rt data or sclk output bus. when ser/ par is high, this pin, part of the serial port, is used as a serial data clock input or output, depending upon the logic state of the ext/ int pin. the active edge where the data sdout is updated depends upon the logic state of the invsclk pin. 23 d10 or sync do when ser/ par is low, this output is us ed as bit 10 of the parallel port data output bus. when ser/ par is high, this output, part of the serial port, is used as a digital output frame synchronization for use with th e internal data clock (ext/ int = logic low). when a read sequence is initiated and invsync is low, sy nc is driven high and remains high while the sdout output is valid. when a read sequence is initiated and invs ync is high, sync is driven low and remains low while the sdout output is valid. 24 d11 or rderror do when ser/ par is low, this output is used as bit 11 of the parallel port data output bus. when ser/ par and ext/ int are high, this output, part of the serial port, is used as an incomplete read error flag. in slave mode, when a data read is started an d not complete when the following conversion is complete, the current data is lo st and rderror is pulsed high. 25C28 d[12:15] do bit 12 to bit 15 of the parallel port data output bus. these pins ar e always outputs regardless of the state of ser/ par . 29 busy do busy output. transitions high when a conversion is started and rema ins high until the conversion is complete and the data is latched into the on-chip shift registe r. the falling edge of busy could be used as a data ready clock signal. 30 dgnd p must be tied to digital ground. 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the external clock. 33 reset di reset input. when set to a logic high, this pin rese ts the ad7667 and the current conversion, if any, is aborted. if not used, this pin could be tied to dgnd. 34 pd di power-down input. when set to a logic high, pow er consumption is reduced and conversions are inhibited after the current one is completed. 35 cnvst di start conversion. if cnvst is high when the acquisition phase (t 8 ) is complete, the next falling edge on cnvst puts the internal sample/hold into the hold state and initiates a conversion. the mode is most appropriate if low sampling jitter is desired. if cnvst is low when the acquisition phase (t 8 ) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. 37 ref ai/o reference input voltage. on-chip reference output voltage. 38 refgnd ai reference input analog ground. 39 ingnd ai analog input ground. 43 in ai primary analog input with a range of 0 v to 2.5 v.
ad7667 rev. 0 | page 10 of 28 pin no. mnemonic type 1 description 45 temp ao temperature sensor voltage output. 46 refbufin ai/o reference input voltage. the re ference output and the reference buffer input. 47 pdref di this pin allows the choice of internal or external voltage references. when low, the on-chip reference is turned on. when high, the internal reference is switched off and an exte rnal reference must be used. 48 pdbuf di this pin allows the choice of buffering an internal or external reference with the internal buffer. when low, the buffer is selected. when high, the buffer is switched off. 1 ai = analog input; ai/o = bidirectional analog; ao = analog output; di = digital input; di/o = bidirectional digital; do = digi tal output; p = power.
ad7667 rev. 0 | page 11 of 28 definitions of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. full-scale error the last transition (from 01110 to 01111 in twos comple- ment coding) should occur for an analog voltage 1? lsb below the nominal full scale (2.49994278 v for the 0 v to 2.5 v range). the full-scale error is the deviation of the actual level of the last transition from the ideal level. unipolar zero error the first transition should occur at a level ? lsb above analog ground (19.073 v for the 0 v to 2.5 v range). unipolar zero error is the deviation of the actual transition from that point. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to s /( n + d ) and is expressed in bits by the following formula: enob = ( s /[ n + d ]db C 1.76)/6.02 total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal, and is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst input to when the input signal is held for a conversion. transient response transient response is the time required for the ad7667 to achieve its rated accuracy after a full-scale step function is applied to its input. reference voltage temperature coefficient reference voltage temperature coefficient is derived from the maximum and minimum reference output voltage ( v ref ) measured at t min , t(25c), and t max . it is expressed in ppm/c using the following equation: 6 10 ) C ( ) c 25 ( ) C ) ) c ppm/ ( = min max ref ref ref ref t t v min ( v max ( v tcv where: v ref ( max ) = maximum v ref at t min , t(25c), or t max v ref ( min ) = minimum v ref at t min , t(25c), or t max v ref (25 c ) = v ref at 25c t max = +85c t min = C40c thermal hysteresis thermal hysteresis is defined as the absolute maximum change of reference output voltage after the device is cycled through temperature from either t_hys+ = 25c to t max to 25c t_hysC = 25c to t min to 25c it is expressed in ppm using the following equation: 6 10 ) 25 ( ) _ ( ) 25 ( ) ( ? = c v hys t v c v ppm v ref ref ref hys where: v ref (25 c ) = v ref at 25c v ref (t_hys) = maximum change of v ref at t_hys+ or t_hysC
ad7667 rev. 0 | page 12 of 28 typical performance characteristics 03035-0-005 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 inl (lsb) 0 16384 32768 49152 65536 code figure 5. integral nonlinearity vs. code 03035-0-006 0 0.5 1.0 1.5 2.0 positive inl (lsb) 0 10 20 number of units 15 5 figure 6. typical positive inl distribution (102 units) 03035-0-007 0 10 20 30 number of units 0 0.25 0.50 0.75 1.00 1.25 1.50 positive dnl (lsb) figure 7. typical positive dnl distribution (102 units) 03035-0-008 ?1.0 ?0.5 0 0.5 1.0 1.5 0 16384 32768 49152 65536 code dnl (lsb) figure 8. differential nonlinearity vs. code 03035-0-009 0 20 ?2.0 ?1.5 ?1.0 ?0.5 0 negative inl (lsb) number of units 10 15 5 figure 9. typical negative inl distribution (102 units) 03035-0-010 0 10 20 30 40 50 60 ?1.00 ?0.75 ?0.50 ?0.25 0 negative dnl (lsb) number of units figure 10. typical negative dnl distribution (102 units)
ad7667 rev. 0 | page 13 of 28 03035-0-011 1 344 14654 0 308 113049 15970 116794 0 20000 40000 60000 80000 100000 120000 140000 counts 7ffe 7fff 8000 8001 8002 8003 8004 8005 code in hex f i g u re 11. h i s t og r a m of 2 61, 1 2 0 co nvers i ons of a dc input a t the code t r a n si t i on 03035-0-012 ? 180 ? 160 ? 140 ? 120 ? 100 ?80 ?60 ?40 ?20 0 amp l itude (db of full s c a l e ) 0 100 200 300 400 500 frequency (khz) f s = 1msps f in = 101.11khz snr = 88.9db thd = ? 94.2db sfdr = 94.7db s/[n+d] = 88db f i g u re 12. fft p l ot 03035-0-013 snr s/[n+d] enob 81 82 83 84 85 86 87 88 89 90 91 snr, s/[n+d] (db) 1 1 0 100 1000 frequency (khz) 13.0 13.5 14.0 14.5 15.0 15.5 enob (bits) fi g u r e 1 3 . s n r , s / ( n + d ) , a n d e n o b v s . fr e q u e n c y 03035-0-014 0 35 2602 2958 16 0 51940 56646 146923 0 20000 40000 60000 80000 100000 120000 140000 160000 180000 counts 7ffe 7fff 8000 8001 8002 8003 8004 8005 8006 code in hex f i g u re 14. h i s t og r a m of 2 61, 1 2 0 co nvers i ons of a dc input a t the code c e nt er 03035-0-015 sfdr thd second harmonic third harmonic ? 120 ? 115 ? 110 ? 105 ? 100 ?95 ?90 ?85 ?80 ?75 ?70 thd, harmonics (db) 1 1 0 100 1000 frequency (khz) 20 30 40 50 60 70 80 90 100 110 120 s f dr (db) fi g u r e 1 5 . t h d, h a r m o n i c s , a n d s f d r v s . fr e q u e n c y 03035-0-016 88 89 90 91 ?60 ? 5 0 ? 40 ?30 ? 20 ? 1 0 0 input level (db) snr, s/[n+d] referre d to full-scale (db) snr s/[n+d] f i gure 16. snr and s/[n+d] vs . input l e v e l (referred to f u ll s c ale)
ad7667 rev. 0 | page 14 of 28 03035-0-017 12.5 13.0 13.5 14.0 14.5 15.0 enob ( b it s) 87 88 89 90 92 s nr, s / [n+d] (db) ?5 5 ?35 ? 15 5 2 5 4 5 6 5 85 105 125 snr s/[n+d] enob temperature ( c) 91 f i g u re 17. snr , s / [ n +d], and e n ob v s . t e mpe r at u r e 03035-0-018 ?115 ?110 ?105 ?100 ?55 ? 35 ?15 5 25 45 65 85 105 125 temperature ( c) thd, harmonics (db) thd second harmonic third harmonic f i g u re 18. th d a n d ha r m on ics v s . t e m p er at u r e 03035-0-019 0.001 0.01 0.1 10 100 1000 10000 100000 10 100 1k 10k 100k 1m sampling rate (sps) op e rating curre nts ( a) 1 avdd, warp/normal dvdd, impulse ovdd, all modes dvdd, warp/normal avdd, impulse pdref = pdbuf = high f i gure 19. o p er atin g current v s . s a mp l e ra te 03035-0-020 full-scale error zero error ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 ze ro e rror, full-s cale e rror (ls b ) ?55 ? 35 ? 1 5 5 25 45 65 85 105 125 temperature ( c) f i gure 20. zero e r r o r , f u l l -s c a l e e r r o r w i th r e fe r e nce v s . t e mpe r atu r e 03035-0-021 2.4966 2.4968 2.4970 2.4972 2.4974 2.4976 2.4978 2.4980 2.4982 2.4984 2.4986 2.4988 ?40 ? 20 0 2 0 4 0 6 0 8 0 100 120 t e m p e r a t u r e ( c ) vr ef ( v ) f i g u re 21. t y pic a l r e f e renc e v o lt ag e o u t p ut v s . t e mpe r at ur e ( 3 u n it s ) 03035-0-022 0 5 10 15 20 25 numbe r of units 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 reference drift (ppm/c) f i gure 22. r e ference v o ltage t e mpe r at ur e coeffi ci ent d i stributi on ( 1 0 2 un its)
ad7667 rev. 0 | page 15 of 28 03035-0-023 0 5 10 15 20 25 30 35 40 45 50 0 5 0 100 150 200 c l (pf) t 12 de lay (ns ) ovdd = 2.7v @ 25 c ovdd = 2.7v @ 85 c ovdd = 5v @ 85 c ovdd = 5v @ 25 c f i g u re 23. t y pic a l d e lay v s . l oad cap a c i t a nce c l
ad7667 rev. 0 | page 16 of 28 circuit information sw a comp sw b in ref refgnd lsb msb 32,768c ingnd 16,384c 4c 2c c c 65,536c control logic switches control busy output code 03033-0-020 cnvst figure 24. adc simplified schematic the ad7667 is a very fast, low power, single supply, precise 16-bit analog-to-digital converter (adc). the ad7667 features different modes to optimize performance according to the applications. in warp mode, the part can convert 1 million samples per second (1 msps). the ad7667 provides the user with an on-chip track/hold, successive approximation adc that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. the ad7667 can be operated from a single 5 v supply and can be interfaced to either 5 v or 3 v digital logic. it is housed in either a 48-lead lqfp or a 48-lead lfcsp that saves space and allows flexible configurations as either a serial or parallel inter- face. the ad7667 is pin-to-pin compatible with pulsar adcs and is an upgrade of the ad7666 and ad7661 . converter operation the ad7667 is a successive-approximation adc based on a charge redistribution dac. figure 24 shows a simplified sche- matic of the adc. the capacitive dac consists of an array of 16 binary weighted capacitors and an additional lsb capacitor. the comparators negative input is connected to a dummy capacitor of the same value as the capacitive dac array. during the acquisition phase, the common terminal of the array tied to the comparators positive input is connected to agnd via sw a . all independent switches are connected to the analog input in. thus, the capacitor array is used as a sampling capacitor and acquires the analog signal on in. similarly, the dummy capacitor acquires the analog signal on ingnd. when cnvst goes low, a conversion phase is initiated. when the conversion phase begins, sw a and sw b are opened. the capacitor array and dummy capacitor are then disconnected from the inputs and connected to refgnd. therefore, the differential voltage between in and ingnd captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between refgnd and ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4, v ref /65536). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after this process is completed, the control logic generates the adc output code and brings the busy output low. modes of operation the ad7667 features three modes of operation: warp, normal, and impulse. each mode is best suited for specific applications. warp mode allows the fastest conversion rate, up to 1 msps. however in this mode and this mode only, the full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. if the time between two consecutive conversions is longer than 1 ms (e.g., after power-up), the first conversion result should be ignored. this mode makes the ad7667 ideal for applications where both high accuracy and fast sample rate are required. normal mode is the fastest mode (800 ksps) without any limitations on the time between conversions. this mode makes the ad7667 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. impulse mode, the lowest power dissipation mode, allows power saving between conversions. when operating at 1 ksps, for example, it typically consumes only 130 w. this feature makes the ad7667 ideal for battery-powered applications.
ad7667 rev. 0 | page 17 of 28 tra n sfer f u nctions ta ble 7. out p ut codes a n d i d ea l input volt a g es digital output code (hex) description analo g input straight binary twos complement fsr C1 lsb 2.499962 v ffff 1 7fff 1 fsr C 2 lsb 2.499923 v fffe 7ffe midscale + 1 lsb 1.250038 v 8001 0001 midscale 1.25 v 8000 0000 midscale C 1 lsb 1.249962 v 7fff ffff Cfsr + 1 lsb 38 v 0001 8001 Cfsr 0 v 0000 2 8000 2 us i n g t h e o b / 2c dig i tal in p u t, the ad7667 o f f e rs tw o o u t p u t co din g s: st r a ig h t b i n a r y a n d two s co m p lem e n t . the ls b si ze is v ref /65536, whic h is a b ou t 38.1 5 v . th e ad76 67 s ideal t r a n sfer cha r ac t e r i st ic is sh o w n in f i gur e 25 and t a b l e 7. 000...000 000...001 000...010 111...101 111...110 111...111 adc code (s tra i ght bina ry ) analog input v ref ? 1.5 lsb v ref ? 1 lsb 1l s b 0v 0.5 lsb 1 lsb = v re f / 65536 03033-0-021 1 th i s i s a l so t h e co d e f o r overrange anal og input ( v in C v in g n d above v re f C v re f g nd ). 2 th i s i s a l so t h e co d e f o r underrange analog input (v in below v in g n d ). f i g u re 25. a d c ide a l t r ans f er f u nc t i o n no tes 1 the configuration shown is using the internal reference and internal buffer. 2 the ad8021 is recommended. see driver amplifier choice section. 3 optional low jitter. 4 a 10 f ceramic capacitor (x5r, 1206 size) is recommended (e.g., panasonic ecj3yb0j106m). see voltage reference input section. ad7667 d 3 clock c/ p/d s p serial por t digit al suppl y (3.3v or 5v) dv d d 100nf + 10 f 100nf + 10 f 20 ? 100nf + 10 f analog suppl y (5v) 2.7nf c c 15 ? analog input (0 v t o 2 . 5 v) pd reset impulse warp ser/par ob/2c bu s y sdout sclk ingnd in refgnd ref gnd avdd dgnd d v dd o v dd ognd 03035-0-026 u1 2 pdref pdbuf rd cs byteswap c n vst refbufin 1 100nf c r 4 f i g u re 26. t y pic a l conne c t io n d i ag r a m
ad7667 rev. 0 | page 18 of 28 t y p i c a l c o nnec t i o n di a g r a m f i gur e 26 s h o w s a typ i cal co nn e c tio n dia g ram f o r th e ad7667. analog input f i g u re 2 7 show s an e q u i v a l e n t c i rc u i t of t h e i n put st r u c t u r e of th e ad7667. the tw o dio d es, d1 a nd d2, p r o v ide e s d p r o t e c t i o n fo r t h e a n alog in p u ts in an d i n g n d . c a r e m u s t be ta k e n t o en s u r e tha t t h e a n alog in p u t sig n al ne ver exce e d s th e su p p l y ra ils b y m o r e t h an 0.3 v . this w i l l ca us e t h es e dio d es t o b e come fo r w a r d-b i as e d a nd st a r t co nd u c t i n g c u r r en t. t h es e dio d es can ha ndle a f o r w a r d-b i as e d c u r r en t o f 100 ma maxim u m. f o r in s t an c e , t h es e c o n d i t io ns co u l d e v en t u al l y o c c u r w h e n t h e in p u t b u f f er s (u1) s u p p lies a r e dif f er en t f r o m a v d d . i n s u ch a cas e , an i n p u t b u f f er wi t h a sh or t-cir c ui t c u r r e n t limi t a t i on can b e u s ed t o p r o t ect t h e pa rt . c2 r1 d1 d2 c1 in or ingnd agnd av d d 03033-0-023 f i g u re 27. equiv a le nt a n al og input c i rcuit this a n alog in pu t s t r u c t ur e al lo ws t h e s a m p l i n g o f t h e dif f er en- tial sig n al betw e e n in and ing n d . u n li k e o t her co n v er t e rs, in gnd is s a m p led a t t h e s a m e time as i n . b y usin g this d i f f er en ti al i n p u t , sm all si gn als co m m o n t o bo th i n p u ts a r e re j e c t e d , a s s h ow n i n fi g u re 2 8 , w h i c h re pre s e n t s t h e t y pi c a l cmrr o v er f r e q uen c y wi t h o n -chi p and ext e r n al r e fer e n c es. f o r in s t an ce , b y usin g in gnd to s e n s e a r e m o te sig n al g r o u nd , g r o u n d p o t e n t ia l dif f er en ces b e t w e e n t h e s e n s o r a nd t h e lo cal ad c g r o u nd a r e e l im ina t e d . 03035-0-028 30 35 40 45 50 55 60 65 70 75 80 1 1 0 100 1000 10000 frequency (khz) cmrr (db) ext ref ref fi g u r e 2 8 . a n a l o g i n p u t c m r r v s . fr e q u e n c y d u r i n g t h e ac quisi t io n phas e , t h e im p e dan c e of t h e a n alog in p u t in c a n be m o de led as a p a ral l e l co m b ina t io n o f ca p a c i t o r c1 a nd t h e n e t w o r k fo r m e d b y t h e s e r i es co nne c t i o n o f r1 and c2. c1 is p r ima r il y th e p i n ca p a ci tan c e . r1 is ty p i cal l y 168 ? a nd is a l u m p e d co m p on e n t ma de u p o f s o me s e r i a l r e sisto r s a nd t h e o n r e sist a n ce o f t h e s w i t ch es. c2 is typ i cal l y 60 pf a n d is ma inl y t h e a d c s a m p lin g ca p a ci t o r . d u r i n g t h e con v ersio n phas e , w h er e t h e sw i t ch es a r e op ene d , t h e i n p u t im p e dan c e is limi te d t o c1. r 1 a nd c2 ma k e a 1-p o le lo w-p a s s f i l t er tha t r e d u ces undesira b l e aliasin g ef fe c t an d limi ts the n o is e . w h en t h e s o ur c e im p e dan c e o f t h e dr ivi n g cir c ui t is lo w , t h e ad7667 can be dr i v en dir e c t l y . l a rg e s o ur ce im p e dan c es sig n ifca n t l y a f fe c t t h e ac p e r f o r ma nce , es p e c i al ly t o t a l ha r m o n i c disto r t i o n ( t h d ). the max i m u m s o ur ce i m p e dan c e dep e n d s on t h e a m ou n t of t h d t h at c a n b e to l e r a t e d. t h e t h d deg r ades as a f u n c t i on o f t h e s o ur ce im p e d a n c e a nd t h e max i m u m in p u t f r e q uen c y , as sh o w n i n f i gur e 29. 03035-0-029 ? 110 ? 100 ?90 ?80 ?70 ?60 ?50 thd (db) 1 1 0 100 1000 input frequency (khz) r s = 20 ? r s = 500 ? r s = 50 ? r s = 100 ? f i g u re 29. th d v s . a n al og input f r equ e nc y and s o urc e r e s i s t anc e driver amplifi e r choice al th o u g h the ad7667 is easy to dr i v e , th e dr i v er a m p l if ier n e e d s t o m e et t h e fol l o w in g r e quir em e n ts: ? the dr i v er am p l if ier a nd the ad7667 a n alog in p u t cir c ui t m u s t be a b le t o s e t t le f o r a f u l l -s cale s t ep o f t h e ca p a c i t o r a r ra y a t a 16-b i t lev e l (0.0015%) . i n the a m p l if ier s da ta s h e e t, s e t t lin g a t 0.1% t o 0.01% is m o r e co mmonl y s p eci- f i e d . this co u l d dif f er sig n if ica n t l y f r o m t h e s e t t lin g t i m e a t a 1 6 - bi t l e vel and s h ou l d b e ve r i f i e d pr i o r to dr ive r se l e cti o n . t h e tin y o p a m p ad8 021 , w h i c h c o m b i n e s u l t r a lo w n o is e and h i g h ga i n -b a ndw id t h , m e e t s t h is s e t t ling ti m e r e q u i r em en t ev e n w h e n used w i t h ga i n s u p t o 13.
ad7667 rev. 0 | page 19 of 28 ? the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transition noise performance of the ad7667. the noise coming from the driver is filtered by the ad7667 analog input circuit 1-pole low-pass filter made by r1 and c2 or by the external filter, if one is used. the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 3 ) ( 2 784 28 log 20 n db loss ne f snr where: f C3db is the input bandwidth of the ad7667 (13 mhz) or the cutoff frequency of the input filter (3.9 mhz), if one is used. n is the noise factor of the amplifier (+1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. for instance, a driver with an equivalent input noise of 2 nv/hz, like the ad8021 with a noise gain of +1 when configured as a buffer, degrades the snr by only 0.13 db when using the filter in figure 26 and by 0.43 db without. ? the driver needs to have a thd performance suitable to that of the ad7667. figure 15 gives the thd versus frequency that the driver should exceed. the ad8021 meets these requirements and is appropriate for almost all applications. the ad8021 needs a 10 pf external compensation capacitor that should have good linearity as an npo ceramic or mica type. moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. the ad8022 could also be used if a dual version is needed and gain of 1 is present. the ad829 is an alternative in applications where high frequency (above 100 khz) performance is not required. in gain of 1 applications, it requires an 82 pf compensation capacitor. the ad8610 is an option when low bias current is needed in low frequency applications. voltage reference input the ad7667 allows the choice of either a very low temperature drift internal voltage reference or an external 2.5 v reference. unlike many adcs with internal references, the internal reference of the ad7667 provides excellent performance and can be used in almost all applications. to use the internal reference along with the internal buffer, pdref and pdbuf should both be low. this produces 1.2 v on refbufin which, amplified by the buffer, results in a 2.5 v reference on the ref pin. the output impedance of refbufin is 11 k? (minimum) when the internal reference is enabled. it is necessary to decouple refbufin with a ceramic capacitor greater than 10 nf. thus the capacitor provides an rc filter for noise reduction. to use an external reference along with the internal buffer, pdref should be high and pdbuf should be low. this powers down the internal reference and allows the 2.5 v reference to be applied to refbufin. to use an external reference directly on ref pin, pdref and pdbuf should both be high. pdref and pdbuf power down the internal reference and the internal reference buffer, respectively. note that the pdref and pdbuf input current should never exceed 20 ma. this could eventually occur when input voltage is above avdd (for instance, at power-up). in this case, a 100 ? series resistor is recommended. the internal reference is temperature compensated to 2.5 v 7 mv. the reference is trimmed to provide a typical drift of 3 ppm/c . this typical drift characteristic is shown in figure 22. for improved drift performance, an external reference, such as the ad780 , can be used. the ad7667 voltage reference input ref has a dynamic input impedance; it should therefore be driven by a low impedance source with efficient decoupling between the ref and refgnd inputs. this decoupling depends on the choice of the voltage reference but usually consists of a low esr tantalum capacitor connected to ref and refgnd with minimum parasitic inductance. a 10 f (x5r, 1206 size) ceramic chip capacitor (or 47 f tantalum capacitor) is appropriate when using either the internal reference or one of these recommended reference voltages: ? the low noise, low temperature drift adr421 and ad780 ? the low power adr291 ? the low cost ad1582
ad7667 rev. 0 | page 20 of 28 for applications that use multiple ad7667s, it is more effective to use the internal buffer to buffer the reference voltage. care should be taken with the voltage references temperature coefficient, which directly affects the full-scale accuracy if this parameter matters. for instance, a 15 ppm/c temperature coefficient of the reference changes full scale by 1 lsb/c. note that v ref can be increased to avdd C 1.85 v. since the input range is defined in terms of v ref , this would essentially increase the range to 0 v to 3 v with an avdd above 4.85 v. the ad780 can be selected with a 3 v reference voltage. the temp pin, which measures the temperature of the ad7667, can be used as shown in figure 30. the output of temp pin is applied to one of the inputs of the analog switch (e.g., adg779 ), and the adc itself is used to measure its own temperature. this configuration is very useful for improving the calibration accuracy over the temperature range. adg779 ad8021 c c 03035-0-024 analog input (unipolar) ad7667 in temperature sensor temp figure 30. temperature sensor connection diagram power supply the ad7667 uses three power supply pins: an analog 5 v supply avdd, a digital 5 v core supply dvdd, and a digital input/ output interface supply ovdd. ovdd allows direct interface with any logic between 2.7 v and dvdd + 0.3 v. to reduce the supplies needed, the digital core (dvdd) can be supplied through a simple rc filter from the analog supply, as shown in figure 26. the ad7667 is independent of power supply sequencing once ovdd does not exceed dvdd by more than 0.3 v, and is thus free of supply voltage induced latch-up. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 31, which represents psrr over frequency with on chip and external references. 03035-0-031 int ref ext ref 30 35 40 45 50 55 60 65 70 75 80 1 10 100 1000 10000 frequency (khz) psrr (db) figure 31. psrr vs. frequency power dissipation versus throughput when using the impulse mode of operation (impulse = high, warp = low), operating currents are very low during the acquisition phase, allowing significant power savings when the conversion rate is reduced (see figure 32). the ad7667 automatically reduces its power consumption at the end of each conversion phase. this makes the part ideal for very low power battery applications. the digital interface and the reference remain active even during the acquisition phase. to reduce operating digital supply currents even further, digital inputs need to be driven close to the power supply rails (i.e., dvdd or dgnd), and ovdd should not exceed dvdd by more than 0.3 v. 03035-0-032 10 100 1k 10k 1m 10 100 1k 10k 100k 1m sampling rate (sps) power dissipation ( w) warp mode power pdref = pdbuf = high 100k impulse mode power figure 32. power dissipati on vs. sampling rate
ad7667 rev. 0 | page 21 of 28 co n v e r s i o n co n t r o l f i g u r e 33 s h o w s th e d e ta ile d tim i n g dia g ra m s o f th e co n v e r s i o n p r o c es s. th e ad7667 is co n t r o l l ed b y th e cnv s t sig n al , whic h ini t i a t e s con v ers i o n . once ini t ia te d , i t ca nn ot b e r e st a r t e d o r a b o r t e d , e v e n b y t h e p o w e r - down in p u t p d , u n t i l t h e con v ersi o n is co m p let e . cnv s t o p era t es i n dep e n d en t l y o f cs and rd . i n i m p u ls e m o de , co n v ersio n s c a n b e a u t o ma t i c a l l y ini t i a te d . i f cnv s t is h e l d lo w w h en b u s y is lo w , th e ad766 7 co n t r o ls t h e ac q u isi t ion phas e and a u t o ma t i c a l l y ini t i a tes a ne w co n- v e rsio n. b y k e epin g cnv s t l o w , t h e ad7667 k e eps the co n v ersio n p r o c es s r u nnin g b y i t s e lf. i t sh o u ld b e n o t e d t h a t t h e a n alog in p u t m u s t be s e t t le d w h en b u s y g o es l o w . also , a t po w e r - u p , cnv s t s h o u ld be b r o u gh t lo w o n ce t o ini t ia t e t h e co n v ersio n p r o c es s. i n this m o de , th e ad7667 c a n r u n s l ig h t l y fas t er than the g u a r a n t e e d 666 ks ps lim i ts in i m p u ls e m o de . this fe a t ur e do e s n o t exist in w a r p a n d n o r m a l m o des . al th o u g h cnv s t is a dig i t a l sig n al , i t sh o u ld be desig n ed wi t h s p ec ial ca r e wi t h fast, c l ea n e d ges, a n d lev e ls wi th m i nim u m o v ersh o o t and un dersh o ot o r r i n g in g. the cnv s t trace s h o u l d b e s h ie lde d wi th gr o u n d an d a lo w val u e s e r i al r e sis t o r (e .g., 50 ?) t e r m ina t ion sh ou ld be adde d c l ose t o th e o u t p u t o f th e co m p o n en t tha t d r i v es th i s li n e . f o r a p plica t ion s wher e s n r is c r i t ica l , t h e cnv s t sig n al s h o u l d ha ve ver y lo w jit t er . this ca n b e achie v e d b y usin g a de dic a te d oscil l a t o r f o r cnv s t ge ne r a t i on , or by c l o c k i ng cnv s t wi t h a high f r eq uen c y , lo w ji t t e r c l o c k, as sh o w n in f i gur e 26. bu s y mode t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 a c q uire conver t a cq uire convert 03033-0-026 cnvst f i gure 33. bas i c co n v ersi on ti ming t 9 t 8 reset data busy 03033- 0- 027 cnvst f i g u re 34. r e se t ti ming t 1 t 3 t 4 t 11 bu s y da t a bu s cs = rd = 0 t 10 previous conversion d a t a new d a t a 03033- 0- 028 cnvst f i g u re 35. m a s t e r p a r a l l e l d a t a tim i ng f o r r e adi n g (cont i nuous r e ad)
ad7667 rev. 0 | page 22 of 28 digit a l in t e rf a c e the ad7667 has a v e rs a t ile dig i tal in t e r f ace; i t c a n be in t e r f ace d wi t h t h e h o s t sy s t em b y usin g ei th er a ser i al o r a p a ral l e l i n t e rf a c e . t h e se ri a l i n t e rf a c e i s m u l t i p l e x e d o n th e pa r a ll e l d a ta b u s. the ad766 7 dig i tal in t e r f ace als o acco mm o d a t es bo th 3 v a n d 5 v logic b y sim p l y co nn ec t i n g the o v d d s u p p l y p i n o f t h e ad7667 t o t h e h o s t sys t em in ter f ace dig i tal s u p p l y . f i nal l y , b y usin g t h e o b / 2c in p u t p i n , bo th tw os co m p lem e n t o r s t ra i g h t b i na r y co di n g c a n b e us e d . the tw o sig n als, cs an d rd , c o n t r o l t h e i n t e r f a c e . cs an d rd ha v e a si mi l a r ef fe c t b e ca us e t h e y a r e o r d t o g e t h er i n t e r n al ly . w h en a t le ast on e o f t h es e sig n als is hi gh, t h e in t e r f ace o u t p u t s a r e in hi gh im pe d a n c e . u s uall y cs al lo ws th e s e lec t io n o f eac h ad7667 in m u l t icir c u i t a p p l ic a t ion s and is he ld lo w in a sin g le ad7667 desig n . rd is g e n e ral l y used t o en a b le the c o n v e r s i on re su lt on t h e d a t a bu s . p a r a llel interf a c e the ad7667 is co nf igur ed t o us e the p a ral l e l in t e r f ace when se r / pa r is h e l d lo w . th e da t a can be r e ad ei t h er af t e r eac h co n v ersio n , whi c h is d u r i n g t h e n e xt ac q u isi t ion phas e , o r d u r i n g t h e fol l o w i n g con v ersio n , as sh o w n i n f i gur e 36 a n d f i gur e 37, r e sp e c t i v e ly . w h en t h e da t a is r e ad d u r i n g t h e co n v er sio n , h o w e v e r , i t is r e co m m e n d e d tha t i t is r e ad o n l y d u r i n g the f i r s t half o f th e co n v er sio n p h ase . this a v o i ds an y po t e n t i a l f e e d thr o u g h bet w een v o l t a g e tra n s i en t s o n t h e di gi tal in t e r f ace a n d t h e m o st cr i t i c al analog co n v ersio n cir c ui t r y . t h e by t e sw ap p i n al lo ws a gl ue les s in t e r f ace t o a n 8-b i t b u s. a s sh o w n in f i gur e 38, th e ls b b y t e is o u t p u t o n d[7:0] a n d t h e ms b is o u t p u t o n d[15:8] w h en by t e sw ap is l o w . w h en by tes w ap is hi gh, t h e ls b a n d ms b b y t e s a r e swa p p e d and th e ls b is o u t p u t o n d[15:8] and the ms b is ou t p u t o n d[7:0]. b y co n n ectin g b y t e sw a p t o a n a d d r e s s lin e , th e 16-b i t d a ta ca n be r e ad in tw o b y t e s o n ei t h er d[15:8] o r d[7:0]. serial interf a c e the ad7667 is co nf igur ed t o us e the s e r i al in t e r f ace when se r / pa r is h e l d hi gh. th e ad76 67 o u t p u t s 16 b i ts o f da ta , ms b f i rst, o n t h e s d o u t pin. this da t a is sy nchr o n iz e d wi t h t h e 16 clo c k p u ls es p r o v ide d on t h e sc lk p i n. the o u t p u t da t a is va lid o n b o t h t h e r i sin g and f a l l in g e d ges o f t h e d a t a clo c k. current conversion bu s y da t a bus t 12 t 13 03033- 0- 029 rd cs f i gure 36. sl ave p a r a l l e l d a ta tim i ng f o r r e adi n g (r ead a f ter co n v e r t) previous conversion t 1 t 3 t 12 t 13 t 4 bu s y da t a bu s 03033- 0- 030 cnvst, rd cs = 0 f i gure 37. sl ave p a r a l l e l d a ta tim i ng f o r r e adi n g (r ead d u ring con v e r t) cs rd byteswap pins d[15:8] pins d[7:0] hi-z hi-z high byte lo w byte lo w byte high byte hi-z hi-z t 12 t 12 t 13 03033-0-031 f i g u re 38. 8-b i t p a r a l l e l int e r f a c e
ad7667 rev. 0 | page 23 of 28 master serial interf a c e u s ual l y , be ca us e th e ad7667 is us ed wi t h a fas t thr o ug h p u t , t h e m a st er read d u r i n g c o n v er sio n m o de is t h e m o s t r e co mm en - de d s e r i a l m o de. i n t h is m o de, t h e s e r i a l clo c k and d a t a to g g l e a t a p p r o p ria t e i n s t a n t s , m i n i mi zi n g po t e n t i a l f eed t h r o u g h bet w een dig i t a l ac t i vity and cr i t ica l con v ersio n de cisio n s . inter n al cloc k the ad7667 is co nf igur ed t o gen e r a t e and p r o v ide t h e s e r i al da ta c l ock s c lk wh en th e ex t / in t p i n is h e l d lo w . th e ad7667 als o g e n e ra t e s a s y n c sig n al t o indic a te t o th e h o s t when t h e s e r i al da t a is v a lid . the s e r i al clo c k s c lk and t h e s y n c sign al can b e in v e r t e d if desir e d . dep e n d in g o n the rd c/s d in in p u t, th e da t a can be r e ad a f t e r eac h co n v er sio n o r d u r i n g t h e fol l o w in g con v ersio n . f i gur e 39 a n d f i gur e 40 s h o w d e ta ile d ti mi n g d i a g ra m s o f th ese t w o m o d e s. i n read af t e r c o n v ersio n m o de, i t sh o u ld be n o t e d t h a t unli k e in o t h e r mo des, t h e b u s y sig n al r e t u r n s l o w af t e r t h e 16 da t a b i ts a r e p u ls e d ou t an d n o t a t t h e end o f t h e con v ersio n phas e , w h ich r e su lts i n a lo n g er b u s y wi d t h. t 3 bu s y sync sclk sdout t 28 t 29 t 14 t 18 t 19 t 20 t 21 t 24 t 26 t 27 t 23 t 22 t 16 t 15 12 3 1 4 1 5 1 6 d15 d14 d2 d1 d0 x rdc/sdin = 0 invsclk = invsync = 0 t 25 t 30 03033-0-032 cnvst cs, rd ext/int = 0 f i gure 39. mas t e r s e ri al d a ta tim i ng f o r r e adi n g (r ead a f ter co n v e r t) ext/int = 0 rdc/sdin = 1 invsclk = invsync = 0 t 3 t 1 t 17 t 14 t 19 t 20 t 21 t 24 t 26 t 25 t 27 t 23 t 22 t 16 t 15 d15 d14 d2 d1 d0 x 12 3 1 4 1 5 1 6 t 18 bu s y sync sclk sdout 03033-0-033 cnvst cs, rd f i g u re 40. m a s t e r s e ri al d a t a tim i ng f o r r e adi n g (r ead pr ev i o us convers i on duri ng co nve r t )
ad7667 rev. 0 | page 24 of 28 sl a v e serial interf a c e extern al c l oc k the ad7667 is co nf igur ed t o acce p t an ext e r n al l y s u p p lied se ri al d a t a c l oc k o n th e s c lk p i n wh en t h e ex t / in t pi n i s h e l d hi gh. i n t h is m o de , s e v e r a l m e t h o d s can be use d t o r e ad t h e da t a . th e ext e r n al s e r i al clo c k is ga t e d b y cs . w h e n cs an d rd a r e bo th l o w , th e da ta ca n be r e a d a f t e r ea ch co n v e r s i o n o r d u r i n g t h e fol l o w i n g con v ersio n . th e ext e r n al clo c k can b e e i t h e r a c o n t i n u o u s or a d i s c on t i n u ou s c l o c k . a d i s c on t i n u ou s clo c k can b e ei t h er n o r m al ly hi gh o r n o r m al ly l o w w h en inac t i v e . f i gur e 41 a n d f i gur e 4 2 s h o w t h e de t a i l e d t i min g dia g ra m s o f th es e m e tho d s. u s ual l y , bec a us e t h e ad7667 has a lo n g er acq u isi t i o n phas e t h a n c o n v ersio n phas e, t h e da t a a r e r e ad imm e dia t ely a f t e r co n v ersi o n . w h ile t h e ad7 667 is p e r f o r m i n g a b i t decision, i t is im p o r t an t th a t v o l t a g e tra n s i e n t s be a v o i ded o n d i gi tal in p u t / o u t p u t p i n s or d e g r a d a t i o n of t h e c o n v e r s i on re su lt c o u l d o c c u r . t h i s i s p a r t ic u l a r ly im p o r t a n t d u r i n g t h e s e con d half o f t h e con v ersio n p h as e bec a us e t h e ad7667 p r o v ides er r o r co r r ec tio n cir c ui tr y tha t c a n co r r ec t f o r a n im p r o p er b i t decisio n made d u r i n g t h e f i r s t h a l f of t h e c o n v e r s i on ph a s e. f o r t h i s re a s on , it i s r e co mme n d e d t h a t when an exter n a l clo c k is b e in g p r o v ide d , i t is a dis c on t i n u o u s clo c k t h a t is tog g l in g o n ly w h en b u s y is l o w , o r , m o r e im po r t a n tl y , tha t i t d o e s n o t tra n s i ti o n d u ri n g t h e l a t t er half o f b u s y hi g h . sclk sdout d15 d14 d1 d0 d13 x15 x 1 4 x13 x1 x0 y15 y14 bu s y sdin invsclk = 0 t 35 t 36 t 37 t 31 t 32 t 16 t 33 x15 x 1 4 x 1 2 3 1 4 1 51 61 7 1 8 t 34 03033-0-034 ext/int = 1 rd rd = 0 f i gure 41. sl ave s e r i a l d a t a tim i ng f o r r e ading (r ead a f te r co n v e r t) s dout sclk d1 d0 x d15 d14 d13 12 3 1 4 1 5 1 6 t 3 t 35 t 36 t 37 t 31 t 32 t 16 bu s y ext/int = 1 invsclk = 0 03033-0-035 cnvst cs rd = 0 f i gure 42. sl ave s e r i a l d a t a tim i ng f o r r e ading (r ead p r e v ious con v ers i on d u ring con v e r t)
ad7667 rev. 0 | page 25 of 28 extern al discontinuous clo c k data read after conv ersion th o u g h t h e maxim u m t h r o ug h p u t cann o t be ac hie v e d usin g this m o de , i t is t h e m o s t r e co mm en ded o f t h e s e r i al s l a v e m o de s. f i gur e 41 sh o w s t h e de t a i l e d t i min g di ag r a m s o f t h is me t h o d . af te r a c o n v e r s i on i s c o m p l e te, i n di c a te d b y b u s y re tu r n i n g l o w , t h e c o n v e r s i on re su lt c a n b e re a d w h i l e b o t h cs an d rd a r e l o w . da t a is s h if t e d o u t ms b f i r s t wi t h 16 c l o c k p u ls es a n d is va l i d o n t h e r i sin g a n d f a l l in g e d ge s o f t h e clo c k. am o n g t h e ad v a n t a g es o f t h is m e t h o d is t h e fac t t h a t con v er - sio n p e r f o r ma nce is n o t deg r ade d b e c a us e t h ere a r e n o v o l t a g e t r a n sien ts on t h e dig i t a l i n t e r f ac e d u r i n g t h e con v ersio n p r o c e ss. an o t h e r ad v a n t a g e is t h e ab i l i t y to r e ad t h e d a t a a t an y sp e e d u p t o 40 mh z, w h ic h acco mm o d a t es bo th t h e s l o w digi tal h o st in t e r f ace a n d t h e fast e s t s e r i al re ading. f i nal l y , in this m o de o n l y , the ad7667 p r o v ides a da isy-c h a i n fe a t ur e usin g t h e rd c/s d in p i n fo r cas c ading m u l t i p le con- v e r t ers t o g e t h er . this fe a t ur e is us ef u l fo r r e d u cin g co m p on e n t co un t and wir i ng co nnec t io n s when desir e d , as, f o r in s t a n ce , in i s o l at e d mu l t i c o n v e r t e r ap p l i c at i o n s . an exa m ple o f t h e conca t ena t ion o f tw o de vi ces is sh o w n i n f i gur e 43. s i m u l t a n e o us s a m p lin g is p o s s ib le b y usin g a co mm o n cnv s t sign al . i t s h o u ld be n o t e d tha t t h e rd c/s d i n in p u t is l a t c h e d o n t h e o p p o si te e d g e o f sclk of t h e on e us e d to shif t o u t t h e da t a o n sd o u t . th er efo r e , t h e m s b o f t h e u ps tr ea m co n v e r t e r j u s t f o llo w s th e l s b o f th e d o w n s tr ea m co n v er t e r o n t h e n e xt sc lk c y cle . sclk sdout rdc/sdin bu s y bu s y data out ad7667 #1 (do wnstream) busy out sclk ad7667 #2 (upstream) rdc/sdin sdout sclk in cnvst in 03035- 0- 036 cnvst cs cnvst cs cs in f i g u re 43. t w o a d 7 6 6 7 s in a d a is y- ch ain conf ig ur at i o n extern al cloc k dat a r e ad d u ring con v e r sion f i g u r e 42 s h o w s th e d e ta ile d tim i n g dia g ra m s o f th i s m e t h o d . dur i n g a co n v er si o n , wh ile bo t h cs an d rd a r e l o w , t h e r e su l t o f t h e p r e v io us co n v ersio n can b e r e ad . th e da t a is shif t e d ou t ms b f i rst wi t h 16 clo c k p u ls es, a n d is vali d o n b o t h t h e r i sin g a n d fal l in g edg e s o f th e c l o c k. th e 16 b i ts m u s t be r e ad b e f o r e t h e c u r r en t con v ersio n is co m p let e ; o t h e r w i s e , rd err o r is pu l s e d hig h and c a n b e u s e d to i n te r r u p t t h e ho st i n te r f ac e to p r e v en t i n com p let e da t a r e adi n g. th er e is n o da isy-cha i n fe a t u r e in t h is m o de and t h e rd c/s d i n in p u t sh o u ld a l wa ys b e t i e d ei t h er hi gh o r l o w . t o r e du c e p e r f o r m a n c e d e g r a d at i o n du e t o d i g i t a l a c t i v i t y , a f a s t d i s c on t i n u ou s c l o c k ( a t l e a s t 1 8 m h z w h e n i m pu l s e mo d e i s u s ed , 25 m h z wh en n o rm al m o d e i s u s ed , o r 40 m h z wh e n w a r p m o de is used) is r e co mm en ded t o en s u r e tha t al l t h e b i ts a r e r e ad d u r i n g t h e f i rst half o f t h e con v ersion phas e . i t is als o p o ss ibl e to b e g i n to re ad d a t a af te r c o n v e r s i on and c o n t i n u e to r e ad t h e last b i t s a f t e r a ne w con v ersio n has b e en ini t ia t e d . thi s al lo ws t h e us e of a slo w er clo c k sp e e d li k e 14 m h z i n i m p u ls e m o de , 18 mh z in n o r m al m o de, a n d 25 mh z in w a r p m o de .
ad7667 rev. 0 | page 26 of 28 micr oprocessor interf a c ing the ad7667 is ideal l y s u i t e d fo r tradi t io nal dc m e as ur em en t ap p l i c at i o n s s u p p o r t i n g a m i c r o p r o c e s s o r , a n d f o r a c s i g n a l p r oce s si n g a p p l ica t i o n s in t e rfa c in g t o a di gi tal sign al p r oce s so r . the ad7667 is desig n e d t o in t e r f ace ei ther wi t h a p a ral l e l 8-b i t o r 16-b i t wide in t e r f ace , o r wi t h a g e n e ral-p u r p ose ser i al p o r t o r i / o p o r t s on a m i c r o c on t r o l l e r . a v a r i e t y of e x te r n a l bu f f e r s c a n be us e d wi t h the ad7667 t o p r ev en t dig i tal n o is e f r o m co u p ling in t o t h e ad c. th e fol l o w in g s e c t io n dis c uss e s t h e us e o f an ad7667 wi t h an ads p -219x s p i eq ui p p e d ds p . spi interface ( a dsp-219x) f i gur e 44 s h o w s a n in t e r f ace diag ra m betw e e n t h e ad7667 and th e s p i eq u i p p e d ads p -219x. t o acco mm o d a t e th e s l o w er s p ee d o f th e ds p , th e ad7667 ac ts as a sla v e de vice and da ta m u s t be r e ad a f ter co n v er sio n . this m o de also al lo ws th e da isy- cha i n fe a t ur e . th e con v er t co mma n d c a n b e ini t ia t e d in re sp ons e to an i n te r n a l t i me r i n te r r u p t . the re a d i n g pro c e s s c a n be in i t ia t e d in r e s p o n s e t o th e en d - o f - c o n v e r s i o n si gn al (b us y g o in g lo w ) usin g a n in t e r r u p t lin e o f t h e ds p . the s e r i al in ter - face (s p i ) o n t h e ads p -219x is co nf igur ed fo r m a s t er m o de (ms t r) = 1, c l o c k p o la r i ty b i t (cpo l) = 0, c l o c k p h as e b i t (cp h a) = 1, a n d s p i i n t e r r u p t ena b le ( t im o d ) = 00b y wr i t i n g t o t h e sp i co n t r o l r e g i ster (s p i cl tx). t o m e et al l t i mi ng r e q u ir em e n ts, t h e sp i clo c k sho u ld b e li mi t e d t o 17 mb ps, whic h al lo ws i t t o r e ad a n ad c r e s u l t in les s tha n 1 s. w h en a hig h er s a m p li ng ra t e is desir e d , us e o f o n e o f t h e p a ral l e l in t e r f ace m o des is r e co mm e n de d . ad7667* adsp-219x* ser/par pfx misox sckx pfx or tfsx bu s y sdout sclk cnvst ext/int cs rd invsclk dv d d * additional pins omitted for clarity spixsel (pfx) 03035-0-037 f i g u re 44. inte r f a c i n g t h e a d 7 6 6 7 to a n spi inte r f ace
ad7667 rev. 0 | page 27 of 28 application hints bipolar and wider input ranges in some applications, it is desirable to use a bipolar or wider analog input range such as 10 v, 5 v, or 0 v to 5 v. although the ad7667 has only one unipolar range, simple modifications of input driver circuitry allow bipolar and wider input ranges to be used without any performance degradation. figure 45 shows a connection diagram that allows this. component values required and resulting full-scale ranges are shown in table 8. when desired, accurate gain and offset can be calibrated by acquiring a ground and voltage reference using an analog multiplexer (u2), as shown in figure 45. u1 a nalo g input r2 r3 r4 100nf r1 u2 c ref in ingnd ref refgnd ad7667 03035-0-038 c f 15 ? 2.7nf figure 45. using the ad7667 in 16-bit bipolar and/or wider input ranges table 8. component values and input ranges input range r1 (?) r2 (k?) r3 (k?) r4 (k?) 10 v 500 4 2.5 2 5 v 500 2 2.5 1.67 0 v to C5 v 500 1 none 0 layout the ad7667 has very good immunity to noise on the power supplies. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the ad7667 should be designed so the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. digital and analog ground planes should be joined in only one place, preferably underneath the ad7667, or as close as possible to the ad7667. if the ad7667 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the ad7667. running digital lines under the device should be avoided since these couple noise onto the die. the analog ground plane should be allowed to run under the ad7667 to avoid noise coupling. fast switching signals like cnvst or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on different but close layers of the board should run at right angles to each other. this will reduce the effect of crosstalk through the board. the power supply lines to the ad7667 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also important to lower the supplys impedance presented to the ad7667 and to reduce the magnitude of the supply spikes. decoupling ceramic capacitors, typically 100 nf, should be placed on each power supply pinavdd, dvdd, and ovddclose to, and ideally right up against these pins and their corresponding ground pins. additionally, low esr 10 f capacitors should be located near the adc to further reduce low frequency ripple. the dvdd supply of the ad7667 can be a separate supply or can come from the analog supply avdd or the digital interface supply ovdd. when the system digital supply is noisy or when fast switching digital signals are present, if no separate supply is available, the user should connect dvdd to avdd through an rc filter (see figure 26) and the system supply to ovdd and the remaining digital circuitry. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. the ad7667 has five different ground pins: ingnd, refgnd, agnd, dgnd, and ognd. ingnd is used to sense the analog input signal. refgnd senses the reference voltage and, because it carries pulsed currents, should be a low impedance return to the reference. agnd is the ground to which most internal adc analog signals are referenced; it must be connected with the least resistance to the analog ground plane. dgnd must be tied to the analog or digital ground plane depending on the config- uration. ognd is connected to the digital system ground. evaluating the ad7667s performance a recommended layout for the ad7667 is outlined in the eval-ad7667 evaluation board for the ad7667. the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control brd2 .
ad7667 rev. 0 | page 28 of 28 outline dimensions top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc sq seating plane 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 compliant to jedec standards ms-026bbc f i gure 46. 48-l ead q u ad f l atpack (l q f p ) [st - 48] di me nsio ns sho w n i n mi ll im e t e r s pin 1 indicator top view 6.75 bs c s q 7.00 bsc sq 1 48 12 13 37 36 24 25 bottom view 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane paddle connected to agnd. this connection is not required to meet the electrical performances 0. 25 m i n 0. 2 0 r e f compliant to jedec standards mo-220-vkkd-2 f i gure 47. 4 8 -l ead f r a m e chip s c a l e p a ckage (lfcs p ) [c p - 48] di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package option ad7667ast C40c to +85c quad flatpack ( l qfp) st-48 ad7667astrl C40c to +85c quad flatpack ( l qfp) st-48 AD7667ACP C40c to +85c lead frame chip scale (lfcsp) cp-48 AD7667ACPrl C40c to +85c lead frame chip scale (lfcsp) cp-48 eval-ad7667c b 1 e v a l u a t i o n bo ar d eval-control brd2 2 c o n t r o l l e r boar d 1 th i s boa r d ca n b e u s ed a s a st a n da l o n e eva l ua t i on boa r d o r i n con j u n c t i on wi th t h e ev al- c on tr ol br d 2 fo r eva l ua t i on /dem on st ra t i on purpose s . 2 th i s boa r d a l l o ws a pc t o con t r o l a n d c o m m u n i ca t e wi t h all an a l og d e vi ce s e v a l ua t i on boa r ds e n di n g i n t h e cb de s i gn a t ors. ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d03035C0C 1/04(0)

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